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Embedded Test for Processor and Memory Cores in System-on-Chips
BibTeX
@MISC{Tehranipour_embeddedtest,
author = {M. H. Tehranipour and M. Nourani and S. M. Fakhraie and M. R. Movahedin and Z. Navabi},
title = {Embedded Test for Processor and Memory Cores in System-on-Chips},
year = {}
}
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Abstract
Embedded processors are now widely used in system-on-chips. The computational power of such processors and their ease of access to/from other embedded cores can be utilized to test SoCs. The first step, naturally, is to test the processor itself and its memory partner, as all other SoC test activities require both. In this paper, an efficient test architecture is presented to achieve high quality testing of embedded processor and memory cores. Specially, in testing the memory core, we present a test algorithm for bit-oriented memories and its enhanced version for wordoriented memories. The method requires low overhead but provides significant flexibility in terms of fault model, test mechanism and future re-use.
Keyphrases
memory core embedded test computational power embedded core enhanced version significant flexibility fault model wordoriented memory efficient test architecture test mechanism future re-use memory partner first step bit-oriented memory high quality testing test algorithm soc test activity
