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Multithreaded Vector Architectures (1997)
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| Venue: | In HPCA-2 |
| Citations: | 59 - 21 self |
BibTeX
@INPROCEEDINGS{Espasa97multithreadedvector,
author = {Roger Espasa and Mateo Valero},
title = {Multithreaded Vector Architectures},
booktitle = {In HPCA-2},
year = {1997},
pages = {281--290},
publisher = {IEEE Computer Society Press}
}
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Abstract
The purpose of this paper is to show that multithreading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate a selection of the Perfect Club and Specfp92 programs and compare their execution time on a conventional vector architecture with a single memory port and on a multithreaded vector architecture. We devote an important part of this paper to study the interaction between multithreading and main memory latency. This paper focuses on maximizing the usage of the memory port, the most expensive resource in typical vector computers. A study of the cost associated with the duplication of the vector register file is also carried out. Overall, multithreading provides for this architecture a performance advantage of more than a factor of 1.4 for realistic memory latencies, and can drive the utilization of the single memory port as high as 95%. 1 Introduction Recent years have...
Keyphrases
multithreaded vector architecture single memory port typical vector computer realistic memory latency memory port resource utilization important part vector register file execution time specfp92 program introduction recent year vector processor performance advantage perfect club expensive resource conventional vector architecture processor throughput main memory latency
