"... In PAGE 1: ...Table 2. Comparison of special functions Table1 summarizes the new special functions available in GAMS. We mention the equivalent routines in Mathematica, Matlab and Numerical Recipes, Chapter 6[34] in table 2.... ..."

"... In PAGE 8: ...worth noting that there is only one minimally redundant NST algorithm for every radix b. Table1 summarizes the values of , and for these special algorithms, for power of two radices: 2 b 32. Notice that the only possible radix 2 NST division ( = 1, = 0, = 1 2) is Burgess apos; algorithm [7], where rj 1rj 2 are recoded in the following two cases: 11 = 0 1 and 1 1 = 01.... In PAGE 8: ... However, no matter what the analysis is, the quotient-digit selection function comes up to be the same as that of the general development presented in this paper. An algorithm not listed in Table1 and deserving special attention concerns the digit-set D lt;16:10 gt;, because all the digits in such a digit-set can be represented as the sum of two digits from the radix 4 signed-digit-set D lt;4:2 gt; (i.... ..."

"... In PAGE 1: ... This is true des- pite the tremendous investments that are made. A collec- tion of such project failures is shown in Table1 with costs ranging from around $50 million to $5 billion, and the final one, an automation project for dispatching of London Ambulances may have cost 20 lives before it was stopped after 48 hours. Each of these projects represents a substantial investment and would not have been abandon- ed without good reasons.... In PAGE 1: ... The latter indeed appears to be a daunting challenge since the safety of airplanes full of people is a major concern that is not present in many other large engineering projects. While people have attributed the failure of the Advanced Auto- mation System to these problems, the magnitude of fail- ures of the large engineering projects in Table1... ..."

"... In PAGE 3: ... These special values are summa- rized in Table 1. Note that in Table1 the sign bit is undefined when a result is a NaN. Also, infinity and zero are signed.... In PAGE 13: ... The latency of all operators (apart from the logic-assisted, double-precision multipliers on Virtex-4 devices) can be set between 0 and a maximum value that is dependent upon the parameters chosen. The maxi- mum latency of the Floating-Point core is tabulated for a range of width and operation types in Table1 0, Table 11, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, and Table 19. The maximum latency of the divide and square root operations is fraction width + 4, and for compare operation it is three cycles.... In PAGE 13: ...2.0 to increase maximum clock frequency. If the previous maximum latency value is specified, then an equivalent implementation will be obtained. Table1 0: Latency of Floating-Point Multiplication using Logic Only Fraction Width Maximum Latency (clock cycles) 4 to 5 5 6 to 11 6 12 to 23 7 24 to 47 (single) 8 48 to 64 (double) 9 Table 11: Latency of Floating-Point Multiplication using MULT18X18S Fraction Width Maximum Latency (clock cycles) 4 to 17 4 18 to 34 (single) 6 35 to 51 7 52 to 64 (double) 8 Table 12: Latency of Floating-Point Multiplication using DSP48 Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 34 (single) 91 1. Single precision only 10 11 35 to 51 15 16 52 to 64 (double) 172 2.... In PAGE 13: ...2.0 to increase maximum clock frequency. If the previous maximum latency value is specified, then an equivalent implementation will be obtained. Table 10: Latency of Floating-Point Multiplication using Logic Only Fraction Width Maximum Latency (clock cycles) 4 to 5 5 6 to 11 6 12 to 23 7 24 to 47 (single) 8 48 to 64 (double) 9 Table1 1: Latency of Floating-Point Multiplication using MULT18X18S Fraction Width Maximum Latency (clock cycles) 4 to 17 4 18 to 34 (single) 6 35 to 51 7 52 to 64 (double) 8 Table 12: Latency of Floating-Point Multiplication using DSP48 Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 34 (single) 91 1. Single precision only 10 11 35 to 51 15 16 52 to 64 (double) 172 2.... In PAGE 13: ...2.0 to increase maximum clock frequency. If the previous maximum latency value is specified, then an equivalent implementation will be obtained. Table 10: Latency of Floating-Point Multiplication using Logic Only Fraction Width Maximum Latency (clock cycles) 4 to 5 5 6 to 11 6 12 to 23 7 24 to 47 (single) 8 48 to 64 (double) 9 Table 11: Latency of Floating-Point Multiplication using MULT18X18S Fraction Width Maximum Latency (clock cycles) 4 to 17 4 18 to 34 (single) 6 35 to 51 7 52 to 64 (double) 8 Table1 2: Latency of Floating-Point Multiplication using DSP48 Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 34 (single) 91 1. Single precision only 10 11 35 to 51 15 16 52 to 64 (double) 172 2.... In PAGE 14: ...14 Table1 3: Latency of Floating-Point Multiplication using DSP48E Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 24 (single) 81 89 25 to 34 10 11 35 to 41 12 13 42 to 51 15 16 52 to 58 (double) 18 19 59 to 64 22 23 1. Single precision only Table 14: Latency of Floating-Point Addition using Medium Usage and DSP48/DSP48E Fraction Width Maximum Latency (clock cycles) DSP48 DSP48E 24 (single) 16 16 53 (double) 12 15 Table 15: Latency of Floating-Point Addition using Logic on Families Other than Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-II, Virtex-II Pro, Spartan-3E, Virtex-4 4, 5 9 6 to 14 10 15 11 16, 17 12 18 to 29 13 30 to 62 14 63, 64 15 Table 16: Latency of Floating-Point Addition using Logic and Low-Latency Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 single 9 double 9 www.... In PAGE 14: ...14 Table 13: Latency of Floating-Point Multiplication using DSP48E Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 24 (single) 81 89 25 to 34 10 11 35 to 41 12 13 42 to 51 15 16 52 to 58 (double) 18 19 59 to 64 22 23 1. Single precision only Table1 4: Latency of Floating-Point Addition using Medium Usage and DSP48/DSP48E Fraction Width Maximum Latency (clock cycles) DSP48 DSP48E 24 (single) 16 16 53 (double) 12 15 Table 15: Latency of Floating-Point Addition using Logic on Families Other than Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-II, Virtex-II Pro, Spartan-3E, Virtex-4 4, 5 9 6 to 14 10 15 11 16, 17 12 18 to 29 13 30 to 62 14 63, 64 15 Table 16: Latency of Floating-Point Addition using Logic and Low-Latency Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 single 9 double 9 www.xilinx.... In PAGE 14: ...14 Table 13: Latency of Floating-Point Multiplication using DSP48E Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 24 (single) 81 89 25 to 34 10 11 35 to 41 12 13 42 to 51 15 16 52 to 58 (double) 18 19 59 to 64 22 23 1. Single precision only Table 14: Latency of Floating-Point Addition using Medium Usage and DSP48/DSP48E Fraction Width Maximum Latency (clock cycles) DSP48 DSP48E 24 (single) 16 16 53 (double) 12 15 Table1 5: Latency of Floating-Point Addition using Logic on Families Other than Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-II, Virtex-II Pro, Spartan-3E, Virtex-4 4, 5 9 6 to 14 10 15 11 16, 17 12 18 to 29 13 30 to 62 14 63, 64 15 Table 16: Latency of Floating-Point Addition using Logic and Low-Latency Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 single 9 double 9 www.xilinx.... In PAGE 14: ...14 Table 13: Latency of Floating-Point Multiplication using DSP48E Fraction Width Maximum Latency (clock cycles) Medium Usage Full Usage Max Usage 4 to 17 6 8 18 to 24 (single) 81 89 25 to 34 10 11 35 to 41 12 13 42 to 51 15 16 52 to 58 (double) 18 19 59 to 64 22 23 1. Single precision only Table 14: Latency of Floating-Point Addition using Medium Usage and DSP48/DSP48E Fraction Width Maximum Latency (clock cycles) DSP48 DSP48E 24 (single) 16 16 53 (double) 12 15 Table 15: Latency of Floating-Point Addition using Logic on Families Other than Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-II, Virtex-II Pro, Spartan-3E, Virtex-4 4, 5 9 6 to 14 10 15 11 16, 17 12 18 to 29 13 30 to 62 14 63, 64 15 Table1 6: Latency of Floating-Point Addition using Logic and Low-Latency Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 single 9 double 9 www.xilinx.... In PAGE 15: ... The DIVIDE_BY_ZERO signal is only available when the divide operation is selected. Table1 7: Latency of Floating-Point Addition using Logic and Speed Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 4 to 13 8 14 9 15 10 16, 17 11 18 to 61 (single, double) 12 62 to 64 13 Table 18: Latency of Fixed-point to Floating-Point Conversion Operand Width Maximum Latency (Cycles) 4 to 8 5 9 to 32 6 31 to 64 7 Table 19: Latency of Floating-Point to Fixed-point Conversion Maximum of (A Fraction Width+1) and Result Width Maximum Latency (Cycles) 44 5 to 16 5 17 to 64 6 tember 28, 2006 www.xilinx.... In PAGE 15: ... The DIVIDE_BY_ZERO signal is only available when the divide operation is selected. Table 17: Latency of Floating-Point Addition using Logic and Speed Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 4 to 13 8 14 9 15 10 16, 17 11 18 to 61 (single, double) 12 62 to 64 13 Table1 8: Latency of Fixed-point to Floating-Point Conversion Operand Width Maximum Latency (Cycles) 4 to 8 5 9 to 32 6 31 to 64 7 Table 19: Latency of Floating-Point to Fixed-point Conversion Maximum of (A Fraction Width+1) and Result Width Maximum Latency (Cycles) 44 5 to 16 5 17 to 64 6 tember 28, 2006 www.xilinx.... In PAGE 15: ... The DIVIDE_BY_ZERO signal is only available when the divide operation is selected. Table 17: Latency of Floating-Point Addition using Logic and Speed Optimization on Virtex-5 FPGAs Fraction Width Maximum Latency (clock cycles) Virtex-5 4 to 13 8 14 9 15 10 16, 17 11 18 to 61 (single, double) 12 62 to 64 13 Table 18: Latency of Fixed-point to Floating-Point Conversion Operand Width Maximum Latency (Cycles) 4 to 8 5 9 to 32 6 31 to 64 7 Table1 9: Latency of Floating-Point to Fixed-point Conversion Maximum of (A Fraction Width+1) and Result Width Maximum Latency (Cycles) 44 5 to 16 5 17 to 64 6 tember 28, 2006 www.xilinx.... ..."