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Abstract

Abstract-- This paper presents a new area efficient, bit-level pipelined, linear systolic array architecture performing exponentiation over large Finite Field GF(2 m). It is based on one multiplier and implements the square-and-multiply algorithm. The architecture is regular, expendable to any field order and programmable with respect to field-generating polynomial P(x). It allows the input elements to enter a linear systolic array in the same order and the system only requires one pipelined control signal. The operations are overlapped at higher system frequency in order to reduce the total delay of the exponentiation computation. A systematic approach is applied for implementing a digit-serial architecture in order to reduce power consumption. The resulting circuit is highly regular and programmable with respect to P(x). An analysis of the performance comparison is described as function of the digit-size. A comparison is made with the bit serial architecture based on the performance improvement with respect to computation delay and power/energy consumption of one exponentiation. Thus, the factor of merit, which could be a measure of performance, is defined as the product of energy times the delay and it is computed. The experimental results on gate level implementations shows that the resulting circuit is lowenergy.