@MISC{_scalablehardware-algorithms, author = {}, title = {Scalable Hardware-Algorithms for Binary Prefix Sums}, year = {} }

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Abstract

AbstractÐIn this work, we address the problem of designing efficient and scalable hardware-algorithms for computing the sum and prefix sums of a wk-bit, k 2, sequence using as basic building blocks linear arrays of at most w2 shift switches, where w is a small power of 2. An immediate consequence of this feature is that in our designs broadcasts are limited to buses of length at most w2. We adopt a VLSI delay model where the ªlengthº of a bus is proportional with the number of devices on the bus. We begin by discussing a hardware-algorithm that computes the sum of a wk-bit binary sequence in the time of 2kÿ 2 broadcasts, while the corresponding prefix sums can be computed in the time of 3kÿ 4 broadcasts. Quite remarkably, in spite of the fact that our hardware-algorithm uses only linear arrays of size at most w2, the total number of broadcasts involved is less than three times the number required by an ªidealº design. We then go on to propose a second hardware-algorithm, operating in pipelined fashion, that computes the sum of a kwk-bit binary sequence in the time of 3k dlogw ke ÿ 3 broadcasts. Using this design, the corresponding prefix sums can be computed in the time of 4k dlogw ke ÿ 5 broadcasts. Index TermsÐHardware-algorithms, shift switching, binary prefix sums, binary counting, scalable architectures, pipelining. æ 1