Abstract

ateri m2/V 551 # A ceived Among these key technologies, we have focused our attention on the low-temperature formation of good quality gate oxide films be-150°C. The process pressure and the radio-frequecy ~rf! power were e Let 0 © T Downlocause the interface between the oxide and silicon has a major effect on the TFT characteristics. Even in securing a 600°C process using a glass substrate, it is not easy to obtain a high-quality gate oxide for a LTPS TFT. Various attempts to grow high-quality gate oxide, SiO2, have been reported, i.e., an electron cyclotron resonance ~ECR! method, an ion plating, an inductively coupled plasma, and a sputtering method.4-7 However, generally, physical deposition meth-ods such as ion plating and sputtering provide poor film uniformity and may result in damage to the interface between the oxide and the Si substrate. In chemical vapor deposition ~CVD! using plasma gen-eration, the successful growth of a high quality gate oxide has not yet been reported at ultralow temperature, 150°C. For depositing a good quality gate oxide with a high uniformity at a low temperature, atomic layer deposition ~ALD! represents a promising method. Moreover, plasma generation to enhance the reactivity of the reac-tant gas is a necessary step in the ALD process, i.e., a plasma-enhanced ~PE! ALD where the growth rate and the film density are dramatically improved. In the PEALD process, advantages of ALD 3 Torr and 300 W, respectively, and total oxide thickness was fixed at 100 nm. In the fabrication of Si TFT devices, the single layer of thermal SiO2, the single layer of PEALD Al2O3, and the stacked layer of thermal SiO2 of 20 nm and PEALD Al2O3 of 80 nm were applied to the gate oxides. The thickness of each gate dielectric was 100 nm. After deposition of the gate dielectrics, a 300 nm thick Al ~1 % Si! and 100 nm TiN metal were deposited sequentially by a sputtering method and then patterned for a gate electrode. A self-aligned N1 implantation was performed at a dose of 5 3 1015/cm2 and an en-ergy of 120 keV. Dopant activation was performed by laser anneal-ing and a 700 nm SiO2 layer was grown by PECVD. Drain current (Id) vs. gate voltage (Vg) curves for n-type Si TFT