Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories

DMCA

Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories (2000)

Cached

Download Links

by Michael Powell , Se-hyun Yang , Babak Falsafi , Kaushik Roy , T. N. Vijaykumar

Citations:

227 - 11 self

BibTeX

@INPROCEEDINGS{Powell00gated-vdd:a,
    author = {Michael Powell and Se-hyun Yang and Babak Falsafi and Kaushik Roy and T. N. Vijaykumar},
    title = {Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories},
    booktitle = {},
    year = {2000},
    pages = {90--95}
}

OpenURL

Abstract

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuitlevel approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V dd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V dd together with a novel resizable cache architecture reduces energy-delay by 62 % with minimal impact on performance. 1

Keyphrases

deep-submicron cache memory circuit technique gated-v dd onchip cache memory supply voltage leakage energy dissipation active cell usage large leakage energy dissipation deep-submicron cmos design large variability unused sram cell novel resizable cache architecture circuit-level technique sram cell minimal impact instruction cache circuitlevel approach

DMCA