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The RR/RR CICQ Switch: Hardware Design for 10-Gbps Link Speed (2003)
| Venue: | In Proceedings, IEEE International Performance, Computing, and Communications Conference |
| Citations: | 14 - 2 self |
BibTeX
@INPROCEEDINGS{Yoshigoe03therr/rr,
author = {Kenji Yoshigoe and Ken Christensen and Aju Jacob},
title = {The RR/RR CICQ Switch: Hardware Design for 10-Gbps Link Speed},
booktitle = {In Proceedings, IEEE International Performance, Computing, and Communications Conference},
year = {2003},
pages = {481--485}
}
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Abstract
The combined input and crossbar queued (CICQ) switch is an input buffered switch suitable for very high-speed networks. The implementation feasibility of the CICQ switch architecture for 24 ports and 10-Gbps link speed is shown in this paper with an FPGA-based design (estimated cost of $30,000 in mid-2002). The bottleneck of a CICQ switch with RR scheduling is the RR poller. We develop a priority encoder based RR poller that uses feedback masking. This design has lower delay than any known design for an FPGA implementation.
