DMCA
A Digital Design Flow for Secure Integrated Circuits (2006)
| Venue: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
| Citations: | 26 - 4 self |
BibTeX
@ARTICLE{Tiri06adigital,
author = {Kris Tiri and Ingrid Verbauwhede},
title = { A Digital Design Flow for Secure Integrated Circuits},
journal = {IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS},
year = {2006},
volume = {25},
number = {7},
pages = {1197--1208}
}
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Abstract
Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal–oxide–semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-µm CMOS.
Keyphrases
digital design flow secure integrated circuit hardware description language design flow sca-resistant layout secure power-analysis-attack-resistant ic key modification full custom layout rule file measurement-based experimental result so-called side-channel attack functional technique smart card digital complementary metal library database electromagnetic radiation direct path power analysis attack resistance extensive simulation differential route procedure execution time prototype advanced encryption standard power consumption differential net iterative design process secure digital design flow large scale normal design side-channel power analysis differential logic style
