3-D Topologies for Networks-on-Chip

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3-D Topologies for Networks-on-Chip (2006)

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by Vasilis F. Pavlidis , Student Member , Eby G. Friedman

Venue:	in Proc. IEEE Int. SOC Conf., 2006
Citations:	65 - 2 self

BibTeX

@INPROCEEDINGS{Pavlidis063-dtopologies,
    author = {Vasilis F. Pavlidis and Student Member and Eby G. Friedman},
    title = {3-D Topologies for Networks-on-Chip},
    booktitle = {in Proc. IEEE Int. SOC Conf., 2006},
    year = {2006},
    pages = {285--288}
}

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Abstract

Abstract—Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3-D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3-D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40 % and 36 % and a decrease of 62 % and 58 % in power consumption is demonstrated for 3-D NoC as compared to a traditional 2-D NoC topology for a network size of aIPVand aPSTnodes, respectively. Index Terms—3-D circuits, 3-D integrated circuits (ICs), 3-D integration, networks-on-chip (NoC), topologies.

Keyphrases

3-d noc 3-d topology power consumption third dimension vertical communication channel physical plane network size communication channel physical constraint zero-load latency novel 3-d structure analytic model traditional 2-d noc topology power consumption model average number functional block maximum number 3-d integration index term 3-d circuit 2-d noc abstract several performance improvement aipvand apstnodes

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