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PTLsim: A cycle accurate full system x86-64 microarchitectural simulator (2007)
| Venue: | in ISPASS ’07 |
| Citations: | 94 - 0 self |
BibTeX
@INPROCEEDINGS{Yourst07ptlsim:a,
author = {Matt T. Yourst},
title = {PTLsim: A cycle accurate full system x86-64 microarchitectural simulator},
booktitle = {in ISPASS ’07},
year = {2007}
}
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Abstract
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 processor core at a configurable level of detail ranging from RTL-level models of all key pipeline structures, caches and devices up to full-speed native execution on the host CPU. Unlike other microarchitectural simulators, PTLsim targets the real commercially available x86 ISA, rather than a discontinued architecture with limited tools and an uncertain future. PTLsim supports several flavors: a single threaded userspace version and a full system version providing an SMT model and the infrastructure for multi-core support. We first describe what it takes to perform cycle accurate modeling of a complete x86 machine at the uop (micro-operation) level, along with the challenges and requirements for effective full system multi-processor capable simulation. We then describe the internal architecture of full system PTLsim and how it interacts with the Xen hypervisor and PTLsim’s native mode co-simulation technology. We experimentally evaluate PTLsim’s real world accuracy by configuring it like an AMD Athlon 64 machine before running a demanding full system client-server networked benchmark inside PTLsim. We compare the statistics generated by our model with the actual numbers from the real processor to demonstrate PTLsim is accurate to within 5 % across all major parameters. We provide a discussion of prior simulation tools, along with their strengths and weaknesses. We describe why PTLsim’s x86 focus is highly relevant, and we use our full system simulation results to demonstrate the pitfalls of userspace only simulation. Finally, we conclude by detailing future work.
Keyphrases
host cpu virtual machine future work complete x86 machine available x86 isa full system ptlsim rtl-level model several flavor modern superscalar prior simulation tool full system version native mode co-simulation technology full-speed native execution internal architecture ptlsim x86 focus actual number configurable level full system client-server networked benchmark limited tool uncertain future major parameter ptlsim real world accuracy multi-core support xen hypervisor key pipeline structure full system simulation result single threaded userspace version real processor microarchitectural simulator order x86-64 processor core ptlsim model discontinued architecture amd athlon smt model
