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Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation (1998)
| Venue: | International Conference on Application of Concurrency to System Design (CSD`98), IEEE Computer Society |
| Citations: | 3 - 1 self |
BibTeX
@INPROCEEDINGS{Velev98verificationof,
author = {Miroslav N. Velev and Al E. Bryant},
title = {Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation},
booktitle = {International Conference on Application of Concurrency to System Design (CSD`98), IEEE Computer Society},
year = {1998},
pages = {200--212}
}
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Abstract
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill’s pipeline verification method [6] to the bit level, is a technique for providing on-the-fly identical initial memory state to two different memory execution sequences. We also present an algorithm which compares the final states of two memories for ternary correspondence, as well as an approach for generating efficiently the initial state of memories. These techniques allow us to verify that a pipelined circuit has behavior corresponding to that of its unpipelined specification by simulating two symbolic ternary execution sequences and comparing their final memory states. Experimental results show the potential of the new ideas. 1.
Keyphrases
symbolic ternary simulation correspondence checking unpipelined specification final state initial state pipeline verification method symbolic ternary execution sequence memory shadowing pipelined circuit new idea on-the-fly identical initial memory state final memory state different memory execution sequence bit level experimental result ternary correspondence
