@MISC{_designof, author = {}, title = {Design of Area Efficient Low Latency Sorting Units}, year = {} }
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Abstract
Abstract- Sorting is an important technique used in many applications such as visual processing unit (VPU), Digital Signal Processing (DSP), network processing etc. To achieve high throughput rates today's computers perform several operations simultaneously. This paper presents the efficient technique for low latency area efficient sorting units. The sorting unit utilizes parallel sorting method which uses compare and exchange blocks. Two popular parallel sorting algorithms are Bitonic sorting network and Odd even sorting network. Using these two sorting networks, it can be shown that the area can be reduced with latency. When input increases, the number of blocks also increases and hence the area increases. To overcome this problem, iterative sorting unit can also be used, in which the inputs are given under looping process. In cases in which I/O bandwidth or area is limited and latency requirements are not stringent, a small max-set-selection unit can be employed using iterative process to obtain the largest values from a given input data set. Such iterative max-set-selection units can provide throughput, latency, and resource requirement tradeoffs. Also to obtain efficient area, the compare and exchange block used in parallel sorting is modified using CMOS comparator. The operation is mainly based on Mux logic and some basic logic gates. Keywords-- Bitonic sorting, latency, odd even sorting, parallel sorting, throughput. I.