BibTeX
@MISC{Anandini_,ram,
author = {Ch. Anandini and F. A. Talukdar},
title = {, Ram Kumar},
year = {}
}
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Abstract
Abstract — This paper presents a 5.7GHz.18-μm CMOS highly linear and good gain LNA which uses an inductive source degeneration topology to increase linear, gain and save power consumption. The circuit measurement is performed using UMC.18μm CMOS Technology in cadence tool. The LNA exhibits a noise figure of2.5dB, gain of 19.6dB, =-18.dB. Also for =-60dBm,-40dBm,-20dBm, IIP3 are-42.55dBm,-22.61dBmand IIP3=-6dBm respectively, while consuming 5.22mW from1.8V.
