BibTeX
@MISC{German08operationclock,
author = {David German},
title = {Operation Clock Cycles},
year = {2008}
}
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Abstract
This report presents an architecture for a specialized digital processor to accelerate evaluation and training of cascade-correlation neural networks by parallelization of multiply-accumulate operations. Design details are given for a prototype with 4 input, 1 output, 16 hidden, and 4 candidate nodes, implemented on an FPGA in communication with a host PC. Table 1 summarizes the performance attained for P training patterns. Technical documentation, issue tracking, and source code for the project is available to the public via a web-based project management tool.1
