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Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels (1997)
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BibTeX
@MISC{Bacis97applicationof,
author = {M. Bacis and G. Buonanno and F. Ferrandi and F. Fummi and L. Gerli and D. Sciuto},
title = {Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels},
year = {1997}
}
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Abstract
ion Levels + M.Bacis, G.Buonanno, F.Ferrandi, F.Fummi, L.Gerli, D.Sciuto Politecnico di Milano, Dipartimento di Elettronica e Informazione. Piazza Leonardo da Vinci, 32. 20133 Milano, ITALY. + The presented methodology is under development in the OMI/ESPRIT 20616 Project -- REQUEST (REuse and QUality ESTimation). Abstract The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. This paper presents a global toolset architecture for testability analysis and test pattern generation. Three abstraction levels are considered in this design flow, from the behavioral specifications, through RTL descriptions, down to gate level. In all these phases, VHDL is chosen as the referring description language. The paper will then present an application scenario, detailing the results achieved by the proposed...
Keyphrases
testing framework different abstraction level early phase project request f.f ummi test problem testability analysis test pattern generation omi esprit global toolset architecture behavioral specification g.b uonanno system design process ion level m.b acis vlsi wsi manufacturer rtl description piazza leonardo da vinci description language quality estimation design flow f.f errandi abstraction level application scenario reliable testability tool d.s ciuto politecnico di milano l.g erli presented methodology
