DMCA
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimdedia terminals
| Venue: | European Solid-State Circuits, 2003, Conference on, 1618 Sept.2003, Pages |
| Citations: | 1 - 0 self |
BibTeX
@INPROCEEDINGS{Woo_alow,
author = {Ramchan Woo and Sungdae Choi and Ju-ho Sohn and Seong-jun Song and Hoi-jun Yoo},
title = {A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimdedia terminals},
booktitle = {European Solid-State Circuits, 2003, Conference on, 1618 Sept.2003, Pages},
year = {},
pages = {53--56}
}
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Abstract
A low-power 3D rendering engine with 2 texture units and 29Mb embedded DRAM is designed and integrated into an LSI for portable 3G multimedia terminals. Texture-mapped 3D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of clock gating, precision-controlled Look-Up Table dividers, texture address alignment and embedded DRAM. The performance is scalable and it reaches up to 100Mpixels/s and 400Mtexles/s at 50MHz. The chip is implemented with 0.16µm pure DRAM process to reduce the fabrication cost. The logic and DRAM consume 46mm2 and 140mW at 33MHz operation. The 3D graphics images are successfully demonstrated by the fabricated chip on the PDA system board. 1.
Keyphrases
low power texture unit multimdedia terminal bilinear mipmap filtering graphic image precision-controlled look-up table divider perspective-correct address calculation multimedia terminal pure dram process pda system board texture address alignment fabrication cost clock gating embedded dram
