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Instruction Pre-Processing in Trace Processors (1999)
| Venue: | In Proceedings of the 5th International Symposium on High Performance Computer Architecture |
| Citations: | 48 - 2 self |
BibTeX
@INPROCEEDINGS{Jacobson99instructionpre-processing,
author = {Quinn Jacobson and Quinn Jacobson and James E. Smith and James E. Smith},
title = {Instruction Pre-Processing in Trace Processors},
booktitle = {In Proceedings of the 5th International Symposium on High Performance Computer Architecture},
year = {1999},
pages = {125--129}
}
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Abstract
In trace processors, a sequential program is partitioned at run time into "traces." A trace is an encapsulation of a dynamic sequence of instructions. A processor that uses traces as the unit of sequencing and execution achieves high instruction fetch rates and can support very wide-issue execution engines. We propose a new class of hardware optimizations that transform the instructions within traces to increase the performance of trace processors. Traces are "pre-processed" to optimize the instructions for execution together. We propose three specific optimizations: instruction scheduling, constant propagation, and instruction collapsing. Together, these optimizations offer substantial performance benefit, increasing performance by up to 24%. 1. Introduction Trace Processors [11] are based on a microarchitecture that encapsulates dynamic instruction sequences into traces at run time. Each trace contains on the order of 16 dynamic instructions and commonly spans multiple basic block...
Keyphrases
trace processor instruction pre-processing run time dynamic instruction dynamic instruction sequence instruction scheduling dynamic sequence new class introduction trace processor substantial performance benefit multiple basic block specific optimization constant propagation wide-issue execution engine sequential program hardware optimization
