BibTeX
@MISC{Vijaykumar98compilingfor,
author = {T. N. Vijaykumar},
title = {Compiling for the Multiscalar Architecture},
year = {1998}
}
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Abstract
High-performance, general-purpose microprocessors serve as compute engines for computers ranging from personal computers to supercomputers. Sequential programs constitute a major portion of real-world software that run on the computers. State-of-the-art microprocessors exploit instruction level parallelism (ILP) to achieve high performance on such applications by searching for independent instructions in a dynamic window of instructions and executing them on a wide-issue pipeline. Increasing the window size and the issue width to extract more ILP may hinder achieving high clock speeds, limiting overall performance. The Multiscalar architecture employs multiple small windows and many narrow-issue processing units to exploit ILP at high clock speeds. Sequential programs are partitioned into code fragments called tasks, which are speculatively executed in parallel. Inter-task register dependences are honored via communication and synchronization and inter-task control flow and memory depe...
Keyphrases
multiscalar architecture high clock speed sequential program real-world software multiple small window major portion wide-issue pipeline inter-task control flow state-of-the-art microprocessor general-purpose microprocessor high performance code fragment compute engine window size personal computer inter-task register dependence independent instruction overall performance instruction level parallelism dynamic window issue width memory depe
