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Experimental Support for Reconfigurable Application-Specific Accelerators
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| Venue: | In Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), in conjuction with the International Symposium on Computer Architecture (ISCA |
| Citations: | 2 - 1 self |
BibTeX
@INPROCEEDINGS{Gelado_experimentalsupport,
author = {Isaac Gelado and Enric Morancho and Nacho Navarro},
title = {Experimental Support for Reconfigurable Application-Specific Accelerators},
booktitle = {In Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), in conjuction with the International Symposium on Computer Architecture (ISCA},
year = {},
pages = {50--57}
}
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Abstract
Abstract—New computer architectures are being proposed and will be implanted in the next few years. A common trend to improve the system performance is to include some reconfigurable logic components into future multi-core chips. Several prototypes already exist but there still is a lack of support from the programming models, the compilers and the operating system. Reconfigurable architectures enable a new execution model based on hardware accelerators. There have been several efforts in the last few years to extend the thread abstraction to include the characteristics of these new reconfigurable elements. the CPU, the inherent model is different from what hardware accelerators should expect. In this paper we present a new way of managing hardware ac-celerators. We propose a new programming and execution model for hardware accelerators based on the processing unit abstrac-tion. We study the relationship between hardware accelerators and the processor architecture, exploring the features that the new reconfigurable architectures should provide to the operating system. We also show how a prototype hardware accelerator achieves a 1.78x speed-up over the software implementation of the same functionality, out of a 41x potential speed-up, due to the data communication overhead. Finally we show our work on dynamic partial reconfiguration and how it enables using the processing unit abstraction to provide virtual reconfigurable logic. I.
Keyphrases
hardware accelerator reconfigurable application-specific accelerator experimental support operating system new reconfigurable element inherent model software implementation last year next year reconfigurable architecture new execution model future multi-core chip system performance several effort processing unit abstraction reconfigurable logic component new reconfigurable architecture programming model processing unit abstrac-tion execution model abstract new computer architecture thread abstraction new way potential speed-up data communication overhead common trend prototype hardware accelerator new programming several prototype dynamic partial reconfiguration processor architecture virtual reconfigurable logic hardware ac-celerators
