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Throughput-Effective On-Chip Networks for Manycore Accelerators (2010)
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BibTeX
@TECHREPORT{Bakhoda10throughput-effectiveon-chip,
author = {Ali Bakhoda and John Kim and Tor M. Aamodt},
title = {Throughput-Effective On-Chip Networks for Manycore Accelerators},
institution = {},
year = {2010}
}
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Abstract
Abstract—As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnec-tion network design. This paper explores throughput-effective network-on-chips (NoC) for future manycore accelerators that employ bulk-synchronous parallel (BSP) programming models such as CUDA and OpenCL. A hardware optimization is “throughput-effective ” if it improves parallel application level performance per unit chip area. We evaluate performance of future looking workloads using detailed closed-loop simulations modeling compute nodes, NoC and the DRAM memory system. We start from a mesh design with bisection bandwidth balanced with off-chip demand. Accelerator workloads tend to demand high off-chip memory bandwidth which results in a many-to-few traffic pattern when coupled with expected technology constraints of slow growth in pins-per-chip. Leveraging these observations we reduce NoC area by proposing a “checker-board ” NoC which alternates between conventional full-routers and half-routers with limited connectivity. Checkerboard em-ploys a new oblivious routing algorithm that maintains a minimum hop-count for architectures that place L2 cache banks at the half-router nodes. Next, we show that increasing network injection bandwidth for the large amount of read reply traffic at the nodes connected to DRAM controllers alleviates a significant fraction of the remaining imbalance resulting from the many-to-few traffic pattern. The combined effect of the above optimizations with an improved placement of memory controllers in the mesh and channel slicing improves application throughput per unit area by 25.4%. Keywords-NoC; Compute accelerator; GPGPU I.
Keyphrases
throughput-effective on-chip network manycore accelerator many-to-few traffic pattern on-chip interconnec-tion network design manycore compute accelerator network injection bandwidth dram controller throughput-effective network-on-chips detailed closed-loop simulation improves application slow growth bisection bandwidth dram memory system bulk-synchronous parallel checker-board noc conventional full-routers technology constraint l2 cache bank compute node parallel application level performance limited connectivity noc area read reply traffic unit chip area future manycore accelerator high off-chip memory bandwidth minimum hop-count unit area memory controller off-chip demand combined effect hardware optimization mesh design significant fraction large amount half-router node improved placement compute accelerator
