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Partial Scan Using Multi-Hop State Reachability Analysis (1999)
| Venue: | in VLSI Test Symp |
| Citations: | 3 - 1 self |
BibTeX
@INPROCEEDINGS{Sharma99partialscan,
author = {Sameer Sharma and Michael S. Hsiao},
title = {Partial Scan Using Multi-Hop State Reachability Analysis},
booktitle = {in VLSI Test Symp},
year = {1999},
pages = {121--126}
}
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Abstract
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting #propagating these target faults. Adding scan to the circuit increases reachability of these hardto -reach and#or previously unreachable states. In this paper, we postulated that fewer scan #ip-#ops are needed to make these states reachable. The states necessary for detecting the hard-to-detect faults, when reached, will facilitate reaching other hard-to-reach states in one or more hops by the sequential test generator, resulting in signi#cantly higher fault coverage. We collect information on the hard-to-reach, aborted, and easy states in our analysis. Results from our approachhave indicated that higher fault coverage can be achieved with signi#cantly fewer scan #ip-#ops for some circuits. I Introduction Partial scan is a DFT technique whichinvolves selecting a subset of #ip-#ops in the circuit for scan. This approach has several advantages ov...
