DMCA
Adding a Vector Unit to a Superscalar Processor (1999)
| Citations: | 22 - 11 self |
BibTeX
@MISC{Quintana99addinga,
author = {Francisca Quintana and Jesus Corbal and Roger Espasa and Mateo Valero},
title = {Adding a Vector Unit to a Superscalar Processor},
year = {1999}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
The focus of this paper is on adding a vector unit to a superscalar core, as a way to scale current state of the art superscalar processors. The proposed architecture has a vector register file that shares functional units both with the integer datapath and with the floating point datapath. A key point in our proposal is the design of a high performance cache interface that delivers high bandwidth to the vector unit at a low cost and low latency. We propose a double-banked cache with alignment circuitry to serve vector accesses and we study two cache hierarchies: one feeds the vector unit from the L1; the other from the L2. Our results show that large IPC values (higher than 10 in some cases) can be achieved. Moreover the scalability of our architecture simply requires addition of functional units, without requiring more issue bandwidth. As a consequence, the proposed vector unit achieves high performance for numerical and multimedia codes with minimal impact on the cycle time of the p...
Keyphrases
vector unit superscalar processor issue bandwidth vector register file minimal impact large ipc value multimedia code key point cache hierarchy high performance point datapath delivers high bandwidth alignment circuitry cycle time art superscalar processor low latency double-banked cache low cost current state share functional unit functional unit high performance cache interface integer datapath superscalar core vector access
