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Razor: A low-power pipeline based on circuit-level timing speculation (2003)
| Venue: | in Proc. IEEE/ACM Int. Symp. Microarchitect |
| Citations: | 288 - 8 self |
BibTeX
@INPROCEEDINGS{Ernst03razor:a,
author = {Dan Ernst and Nam Sung Kim and Shidhartha Das and Sanjay Pant and Rajeev Rao and Toan Pham and Conrad Ziesler and David Blaauw and Todd Austin and Krisztian Flautner and Trevor Mudge},
title = {Razor: A low-power pipeline based on circuit-level timing speculation},
booktitle = {in Proc. IEEE/ACM Int. Symp. Microarchitect},
year = {2003},
pages = {7--18}
}
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Abstract
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities will be very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of a timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in 0.18 µm technology and was analyzed. Razor energy overheads during normal operation are limited to 3.1%. Analyses of a fullcustom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%). 1
Keyphrases
circuit-level timing speculation fast clock supply voltage razor energy overhead critical concern critical voltage worst-case combination new approach timing error silicon integration dynamic detection maximum power saving little impact different variability environmental variation power aware computing conservative supply voltage program state substantial energy saving data dependence worst-case scenario embedded processor poweraware computing dynamic voltage scaling key idea clock frequency latch value prototype razor pipeline spice-level kogge-stone adder model reveal correct operation double-samples pipeline stage value fullcustom multiplier voltage margin razor flip-flop circuit operation circuit timing error normal operation metastability-tolerant comparator circuit delay error rate time-borrowing delayed clock
