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Power Analysis of System-Level On-Chip Communication Architectures (2004)
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by
Kanishka Lahiri
,
Anand Raghunathan
| Citations: | 24 - 0 self |
BibTeX
@MISC{Lahiri04poweranalysis,
author = {Kanishka Lahiri and Anand Raghunathan},
title = {Power Analysis of System-Level On-Chip Communication Architectures},
year = {2004}
}
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Abstract
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption. Various
