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2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains

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by Shianling Wu , Laung-terng Wang , Lizhen Yu , Hiroshi Furukawa , Xiaoqing Wen , Wen-ben Jone , Nur A. Touba , Feifei Zhao , Jinsong Liu , Hao-jan Chao , Fangfang Li , Zhigang Jiang