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Testing High Speed VLSI Devices Using Slower Testers (1999)
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BibTeX
@MISC{Krstic99testinghigh,
author = {Angela Krstic and Kwang-Ting (Tim) Cheng and Srimat T. Chakradhar},
title = {Testing High Speed VLSI Devices Using Slower Testers},
year = {1999}
}
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Abstract
The speed of new VLSI designs is rapidly increasing. Assuring the performance of the circuit requires that the circuit be tested at its intended operating speed. The high cost of high speed testers makes it impossible for the testers to follow the designs in terms of speed increase. This gap between the speed of the new circuits and the speed of the testers is not likely to disappear. In this paper, we focus on at-speed strategies for testing high speed designs on slower testers. Conventional at-speed testing strategies assume that the primary inputs/outputs can be applied/observed at the circuit rated speed. This requires a high speed tester. Our assumption is that a fast clock matching the speed of the designs is available. We describe two classes of at-speed strategies that can be used on a low speed tester. The first class consists of testing schemes for which the test generation procedure is independent of the speed of the tester. These methods apply multiple input patterns in one tester cycle and the test application time for them can be long. The strategies in the second class of at-speed testing schemes integrate the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. We present preliminary experimental results for at-speed schemes for slow testers for transition faults. 1
Keyphrases
at-speed strategy high speed tester test application time test generation process high speed design slow tester fast clock transition fault tester cycle speed increase reduced fault coverage multiple input pattern new circuit test generation procedure low speed tester primary input output first class fault coverage intended operating speed at-speed scheme conventional at-speed testing strategy present preliminary experimental result second class new vlsi design high cost
