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Voltage Screens Early-Life Failures In Cmos Integrated Circuits (1998)
BibTeX
@MISC{Chang98voltagescreens,
author = {Tsung-Yung Jonathan Chang},
title = {Voltage Screens Early-Life Failures In Cmos Integrated Circuits},
year = {1998}
}
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Abstract
This thesis presents the results of a study of screens for detecting weak chips, and reducing intermittent failures and early-life failures. The three screens studied, both theoretically and experimentally, were VLV (Very-Low-Voltage), SHOVE (Short Voltage Elevation) and I DDQ . The study aimed mainly at (1) identifying the defects for which each technique is effective and (2) determining the best parameters to be used when applying each technique. VLV testing is a method where a test is performed at a supply voltage that is much lower than its nominal operating voltage. It can detect resistive shorts and delay flaws that are caused by degraded signals or diminished-drive gates. The supply voltage for VLV testing should be between 2V t and 2.5V t , where V t is the threshold voltage of a transistor. This conclusion was verified in a test chip experiment. We also investigated the defects in CMOS domino circuits and derived the test conditions for them. VLV testing can improve th...
