The MIT Alewife Machine: Architecture and Performance

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The MIT Alewife Machine: Architecture and Performance (1995)

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by Anant Agarwal , Ricardo Bianchini , David Chaiken , David Kranz , John Kubiatowicz , Beng-hong Lim , Kenneth Mackenzie , Donald Yeung

Venue:	In Proceedings of the 22nd Annual International Symposium on Computer Architecture
Citations:	193 - 22 self

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@INPROCEEDINGS{Agarwal95themit,
    author = {Anant Agarwal and Ricardo Bianchini and David Chaiken and David Kranz and John Kubiatowicz and Beng-hong Lim and Kenneth Mackenzie and Donald Yeung},
    title = {The MIT Alewife Machine: Architecture and Performance},
    booktitle = {In Proceedings of the 22nd Annual International Symposium on Computer Architecture},
    year = {1995},
    pages = {2--13}
}

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Abstract

Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Alewife machine, a prototype implementation of the architecture, demonstrates that a parallel system can be both scalable and programmable. Four mechanisms combine to achieve these goals: software-extended coherent shared memory provides a global, linear address space; integrated message passing allows compiler and operating system designers to provide efficient communication and synchronization; support for fine-grain computation allows many processorsto cooperate on small problem sizes; and latency tolerance mechanisms -- including block multithreading and prefetching -- mask unavoidable delays due to communication; Microbenchmarks, together with over a dozen complete applications running on the 32-node prototype, help analyze the behavior of the system. Analysis shows that integrating message passing with sha...

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mit alewife machine software-extended coherent efficient communication 32-node prototype operating system designer constant cost cost-effective mesh network processing node mask unavoidable delay small problem size allows compiler block multithreading parallel system fine-grain computation prototype implementation linear address space many processorsto cooperate dozen complete application multiprocessor architecture latency tolerance mechanism

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