Task Selection for a Multiscalar Processor

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Task Selection for a Multiscalar Processor (1998)

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by T. N. Vijaykumar , Gurindar S. Sohi

Venue:	In Proceedings of the 31st annual international symposium on Microarchitecture
Citations:	70 - 6 self

BibTeX

@INPROCEEDINGS{Vijaykumar98taskselection,
    author = {T. N. Vijaykumar and Gurindar S. Sohi},
    title = {Task Selection for a Multiscalar Processor},
    booktitle = {In Proceedings of the 31st annual international symposium on Microarchitecture},
    year = {1998},
    pages = {81--92}
}

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Abstract

The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without impeding improvements in clock speeds. The main goal of this paper is to understand the key implications of the architectural features of distributed processor organization and task-level speculation for compiler task selection from the point of view of performance. We identify the fundamental performance issues to be: control flow speculation, data communication, data dependence speculation, load imbalance, and task overhead. We show that these issues are intimately related to a few key characteristics of tasks: task size, inter-task control flow, and inter-task data dependence. We describe compiler heuristics to select tasks with favorable characteristics. We report experimental results to show that the heuristics are successful in boosting overall performance by establishing larger ILP win...

Keyphrases

multiscalar processor task selection task-level speculation distributed processor organization control flow speculation multiscalar architecture data communication inter-task control flow compiler heuristic key characteristic compiler task selection high degree task overhead key implication overall performance data dependence speculation instruction level parallelism task size architectural feature inter-task data dependence sequential program main goal fundamental performance issue load imbalance experimental result favorable characteristic clock speed

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