LogP: Towards a Realistic Model of Parallel Computation

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LogP: Towards a Realistic Model of Parallel Computation (1993)

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by David Culler , Richard Karp , David Patterson , Abhijit Sahay , Klaus Erik Schauser , Eunice Santos , Ramesh Subramonian , Thorsten von Eicken

Citations:

555 - 15 self

BibTeX

@INPROCEEDINGS{Culler93logp:towards,
    author = {David Culler and Richard Karp and David Patterson and Abhijit Sahay and Klaus Erik Schauser and Eunice Santos and Ramesh Subramonian and Thorsten von Eicken},
    title = {LogP: Towards a Realistic Model of Parallel Computation},
    booktitle = {},
    year = {1993},
    pages = {1--12},
    publisher = {}
}

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Abstract

A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representatives in the real world. Both kinds of models encourage exploitation of formal loopholes, rather than rewarding development of techniques that yield performance across a range of current and future parallel machines. This paper offers a new parallel machine model, called LogP, that reflects the critical technology trends underlying parallel computers. It is intended to serve as a basis for developing fast, portable parallel algorithms and to offer guidelines to machine designers. Such a model must strike a balance between detail and simplicity in order to reveal important bottlenecks without making analysis of interesting problems intractable. The model is based on four parameters that specify abstractly the computing bandwidth, the communication bandwidth, the communication delay, and the efficiency of coupling communication and computation. Portable parallel algorithms typically adapt to the machine configuration, in terms of these parameters. The utility of the model is demonstrated through examples that are implemented on the CM-5.

Keyphrases

parallel computation realistic model portable parallel algorithm simplistic model communication bandwidth real world computing bandwidth parallel computer specific model machine designer machine configuration new parallel machine model communication delay vast body theoretical research important bottleneck formal loophole future parallel machine critical technology trend

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