A theory of timed automata

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A theory of timed automata (1999)

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by Rajeev Alur

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2650 - 32 self

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@MISC{Alur99atheory,
    author = {Rajeev Alur},
    title = {A theory of timed automata},
    year = {1999}
}

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Abstract

Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of real-time systems whose correctness depends on relative magnitudes of different delays. Consequently, timed automata [7] were introduced as a formal notation to model the behavior of real-time systems. Its definition provides a simple way to annotate state-transition graphs with timing constraints using finitely many real-valued clock variables. Automated analysis of timed automata relies on the construction of a finite quotient of the infinite space of clock valuations. Over the years, the formalism has been extensively studied leading to many results establishing connections to circuits and logic, and much progress has been made in developing verification algorithms, heuristics, and tools. This paper provides a survey of the theory of timed automata, and their role in specification and verification of real-time systems.

Keyphrases

real-time system different delay model checking many result traditional technique formal notation network protocol clock valuation finite quotient simple way practical tool timed automaton relies explicit modeling verification algorithm timing constraint infinite space many real-valued clock variable automated debugging state-transition graph timed automaton complex reactive system much progress relative magnitude embedded controller

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