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Garp: A MIPS Processor with a Reconfigurable Coprocessor (1997)
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@MISC{Hauser97garp:a,
author = {John R. Hauser and John Wawrzynek},
title = {Garp: A MIPS Processor with a Reconfigurable Coprocessor},
year = {1997}
}
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Abstract
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.
Keyphrases
mips processor reconfigurable coprocessor similar technology typical reconfigurable machine exhibit shortcoming garp architecture standard mips processor reconfigurable hardware useful application preliminary performance result novel aspect general-purpose computing prototype software environment
