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Multi-junction fault-tolerance Architecture for Nanoscale Crossbar Memories (2008)
| Venue: | IEEE Transactions on Nanotechnology |
| Citations: | 2 - 2 self |
BibTeX
@ARTICLE{Coker08multi-junctionfault-tolerance,
author = {Ayodeji Coker and Valerie Taylor and Debayan Bhaduri and Eep Shukla and Arijit Raychowdhury and Kaushik Roy},
title = {Multi-junction fault-tolerance Architecture for Nanoscale Crossbar Memories},
journal = {IEEE Transactions on Nanotechnology},
year = {2008},
pages = {202--208}
}
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Abstract
Abstract—Nanoscale elements are fabricated using bottom-up processes, and as such are prone to high levels of defects. Therefore, fault-tolerance is crucial for the realization of practical nanoscale devices. In this paper, we investigate a fault-tolerance scheme that utilizes redundancies in the rows and columns of a nanoscale crossbar molecular switch memory array. In particular, we explore the performance tradeoffs of time delay, power, and reliability for different amounts of redund-ancies. The results indicate an increase in fault-tolerance with small increases in delay and area utility. Index Terms—Crossbar nanomemories, fault tolerance, molecular electronics, nanoelectronics, reliability. I.
Keyphrases
nanoscale crossbar memory multi-junction fault-tolerance architecture utilizes redundancy time delay molecular electronics small increase index term crossbar nanomemories abstract nanoscale element practical nanoscale device fault-tolerance scheme performance tradeoff area utility high level bottom-up process different amount fault tolerance
