Piranha: A scalable architecture based on single-chip multiprocessing

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Piranha: A scalable architecture based on single-chip multiprocessing (2000)

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by Luiz André Barroso , Kourosh Gharachorloo , Robert Mcnamara , Andreas Nowatzyk , Shaz Qadeer , Barton Sano , Scott Smith , Robert Stets , Ben Verghese

Venue:	SIGARCH Comput. Archit. News
Citations:	244 - 7 self

BibTeX

@ARTICLE{Barroso00piranha:a,
    author = {Luiz André Barroso and Kourosh Gharachorloo and Robert Mcnamara and Andreas Nowatzyk and Shaz Qadeer and Barton Sano and Scott Smith and Robert Stets and Ben Verghese},
    title = {Piranha: A scalable architecture based on single-chip multiprocessing},
    journal = {SIGARCH Comput. Archit. News},
    year = {2000},
    pages = {282--293}
}

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Abstract

The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors

Keyphrases

scalable architecture single-chip multiprocessing commercial workload complex processor alternative processor design explicit thread-level parallelism large memory stall time high-performance server design time microprocessor industry on-line transaction processing promising approach semiconductor integration density development cost important market chip multiprocessing commercial application instructionlevel parallelism exhibit little instruction-level parallelism important commercial application

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