Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols

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Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols (2001)

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by Tiberiu Chelcea , Steven M. Nowick

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69 - 2 self

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@MISC{Chelcea01robustinterfaces,
    author = {Tiberiu Chelcea and Steven M. Nowick},
    title = {Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols},
    year = {2001}
}

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Abstract

that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The design are then adapted to work between systems with very long interconnection delays, by migrating a single-clock solution by Carloni et al. (for "latency-insensitive" protocols) to mixedtiming domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.

Keyphrases

latency-insensitive protocol mixed-timing system robust interface connected system long interconnection delay initial simulation interface operating speed single-clock solution different speed interface system new design

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