DMCA
DVFS in Loop Accelerators Using BLADES
| Citations: | 5 - 2 self |
BibTeX
@MISC{Dasika_dvfsin,
author = {Ganesh Dasika and Shidhartha Das and Scott Mahlke and David Bull},
title = {DVFS in Loop Accelerators Using BLADES},
year = {}
}
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Abstract
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operations together. Results on a range of loop accelerators show average energy savings of 32 % gained by voltage scaling below the nominal supply voltage.
Keyphrases
loop accelerator using blade razor flip-flop reduced non-recurring engineering cost loop accelerator stringent energy constraint silicon variation automatic system nominal supply voltage self-tuning hardware accelerator short time-to-market data characteristic primitive computation operation high performance requirement hardware accelerator operating frequency environmental condition embedded system configurable loop accelerator average energy saving voltage scaling better-than-worst-case loop accelerator design
