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An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis (1998)
BibTeX
@MISC{Devadas98analgorithmic,
author = {Srinivas Devadas and Kurt Keutzer},
title = {An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis},
year = {1998}
}
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Abstract
Most approaches to the synthesis of built-in self test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BIST generator is chosenandthen evaluatedby faultsimulating the design with the vectors that the chosengenerator generates. We develop an algorithmic synthesis-during-test approach in this paper, wherein the tasks of synthesizing the BIST logic and directed test pattern generation (DTPG) are intertwined to maximize the resulting fault coverage. Our approach is applicable to a variety of BIST strategies including those that use linear- and nonlinear-feedback shift registers. We show how our method can be used to synthesize LFSR polynomials, LFSR seeds, LFSR weights, nonlinear feedback, or bit-fixing logic. Experimental data is presented. I. INTRODUCTION Built-in Self Test (BIST) has been of interest for some time because it provides in-field testing at request and simplifies fault diagnosis. Recently, with the cost of high-speed VLSI testers increasing wi...
Keyphrases
bist logic synthesis optimizing fault coverage algorithmic approach manual choose-and-evaluate approach particular bist generator built-in self test lfsr weight nonlinear feedback lfsr seed bist logic high-speed vlsi tester bist strategy chosengenerator generates test pattern generation fault coverage introduction built-in self test experimental data algorithmic synthesis-during-test approach nonlinear-feedback shift register lfsr polynomial bit-fixing logic
