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Scaling Performance of Interior-Point Method on Large-Scale Chip Multiprocessor System
| Citations: | 3 - 1 self |
BibTeX
@MISC{Smelyanskiy_scalingperformance,
author = {Mikhail Smelyanskiy and Victor W Lee and Daehyun Kim and Anthony D Nguyen and Pradeep Dubey},
title = {Scaling Performance of Interior-Point Method on Large-Scale Chip Multiprocessor System},
year = {}
}
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Abstract
In this paper we describe parallelization of interior-point method (IPM) aimed at achieving high scalability on large-scale chipmultiprocessors (CMPs). IPM is an important computational technique used to solve optimization problems in many areas of science, engineering and finance. IPM spends most of its computation time in a few sparse linear algebra kernels. While each of these kernels contains a large amount of parallelism, sparse irregular datasets seen in many optimization problems make parallelism difficult to exploit. As a result, most researchers have shown only a relatively low scalability of 4X-12X on medium to large scale parallel machines. This paper proposes and evaluates several algorithmic and hardware features to improve IPM parallel performance on largescale CMPs. Through detailed simulations, we demonstrate how exploring multiple levels of parallelism with hardware support for low overhead task queues and parallel reduction enables IPM to achieve up to 48X parallel speedup on a 64-core CMP. 1.
Keyphrases
interior-point method large-scale chip multiprocessor system hardware support important computational technique detailed simulation sparse irregular datasets low scalability 64-core cmp large scale parallel machine many area large-scale chipmultiprocessors optimization problem many optimization problem high scalability hardware feature computation time sparse linear algebra kernel largescale cmps exploring multiple level parallel reduction low overhead task queue large amount ipm parallel performance
