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Study of Thread Level Parallelism in a Video Encoding Application for Chip Multiprocessor Design
BibTeX
@MISC{Debes_studyof,
author = {Eric Debes and Greg Kaine},
title = {Study of Thread Level Parallelism in a Video Encoding Application for Chip Multiprocessor Design},
year = {}
}
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Abstract
In media applications there is a high level of available thread level parallelism (TLP). In this paper we study the intra TLP in a video encoder. We show that a well-distributed highly optimized encoder running on a symmetric multiprocessor (SMP) system can run 3.2 faster on a 4-way SMP machine than on a single processor. The multithreaded encoder running on an SMP system is then used to understand the requirements of a chip multiprocessor (CMP) architecture, which is one possible architectural direction to better exploit TLP. In the framework of this study, we use a software approach to evaluate the dataflow between processors for the video encoder running on an SMP system. An estimation of the dataflow is done with L2 cache miss event counters using Intel VTune performance analyzer. The experimental measurements are compared to theoretical results.
Keyphrases
chip multiprocessor design thread level parallelism video encoding application video encoder smp system single processor intra tlp experimental measurement l2 cache miss event counter intel vtune performance analyzer 4-way smp machine possible architectural direction medium application chip multiprocessor available thread level parallelism optimized encoder software approach multithreaded encoder symmetric multiprocessor theoretical result high level
