Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration

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Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration (2001)

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by Rongtian Zhang , Kaushik Roy , Cheng-Kok Koh , David B. Janes

Venue:	in Proc. ACM Design Automation Conf
Citations:	11 - 0 self

BibTeX

@INPROCEEDINGS{Zhang01exploringsoi,
    author = {Rongtian Zhang and Kaushik Roy and Cheng-Kok Koh and David B. Janes},
    title = {Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration},
    booktitle = {in Proc. ACM Design Automation Conf},
    year = {2001},
    pages = {846--851}
}

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Abstract

Dimensional (3-D) integration offers numerous advantages over conventional structures. Double-gate (DG) transistors can be fabricated for better device characteristics, and multiple device layers can be vertically stacked for better interconnect performance. In this paper, we explore the suitable device structures and interconnect architectures for multi-device-layer integrated circuits and study how 3-D SOI circuits can better meet the performance and power dissipation requirements projected by ITRS for future technology generations. Results demonstrate that DGSOI circuits can achieve as much as performance gain and power delay product reduction than SGSOI (single-gate SOI). More important, for an interconnect-dominated circuits, multi-device-layer integration offers significant performance improvement. Compared to 2-D integration, most 3-D circuits can be clocked at much higher frequencies (double or even triple). Multi-device-layer circuits, with suitable SOI device structures, can be a viable solution for future low power high performance applications.

Keyphrases

interconnect architecture soi device structure 3-dimensional integration numerous advantage interconnect-dominated circuit 3-d circuit 2-d integration 3-d soi circuit power delay product reduction interconnect performance suitable soi device structure conventional structure device characteristic multi-device-layer circuit multiple device layer viable solution single-gate soi suitable device structure power dissipation requirement performance gain future technology generation dgsoi circuit

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