DMCA
Interconnection Delay and clock Cycle Selection
by
Ix Mecha
,
M. Fernindez
| Venue: | in High-Level Synthesis", 10 Int. Conference on VLSI Design, Ayderabad |
| Citations: | 1 - 0 self |
BibTeX
@INPROCEEDINGS{Mecha_interconnectiondelay,
author = {Ix Mecha and M. Fernindez},
title = {Interconnection Delay and clock Cycle Selection},
booktitle = {in High-Level Synthesis", 10 Int. Conference on VLSI Design, Ayderabad},
year = {},
pages = {4--7}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
This paper presents a method to estimate the delay of interconnections. It uses a simple model based exclusively on point to point interconnections, The method has a very low complexity so it can be used during the clock cycle selection in a High Level Synthesis process. In this way it is possible to settle securely the right electrical behavior of the final circuit 1.
