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Issues and support for dynamic register allocation (2006)
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| Venue: | In Asia-Pacific Computer Systems Architecture Conference |
| Citations: | 1 - 0 self |
BibTeX
@INPROCEEDINGS{Das06issuesand,
author = {Abhinav Das and Abhinav Das and Rao Fu and Rao Fu and Antonia Zhai and Antonia Zhai and Wei-chung Hsu and Wei-chung Hsu},
title = {Issues and support for dynamic register allocation},
booktitle = {In Asia-Pacific Computer Systems Architecture Conference},
year = {2006},
pages = {351--358}
}
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Abstract
Abstract. Post-link and dynamic optimizations have become important to achieve program performance. This is because, it is difficult to produce a single binary that fits all micro-architectures and provides good performance for all inputs. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code with the main program. We show that it is difficult to achieve both correctness and transparency when only software schemes for acquiring registers are used. We then propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. The hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a “safe ” manner, thus preserving the transparency and improving the performance of these systems. 1
