DMCA
A 3D SoC design for H.264 application with on-chip DRAM stacking (2010)
| Venue: | In 3D Systems Integration Conference (3DIC), 2010 IEEE International |
| Citations: | 2 - 0 self |
BibTeX
@INPROCEEDINGS{Zhang10a3d,
author = {Tao Zhang and Kui Wang and Yi Feng and Yan Chen and Qun Li and Bing Shao and Jing Xie and Xiaodi Song and Lian Duan and Yuan Xie and Xu Cheng and Youn-Long Lin},
title = {A 3D SoC design for H.264 application with on-chip DRAM stacking},
booktitle = {In 3D Systems Integration Conference (3DIC), 2010 IEEE International},
year = {2010},
pages = {1--6}
}
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Abstract
Abstract-Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the "memory wall" challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint of I/O pin count. To demonstrate the feasibility of 3D memory stacking, this paper introduces a 3D System-on-Chip (SoC) for H.264 applications that can make use of multiple memory channels offered by 3D integration. Two logic tiers are stacked together with each having an area of 2.5×5.0mm 2 , with a 3-layer 8-channel 3D DRAM stacked on the top. The design flow for this 3D SoC is also presented. The prototype chip has been fabricated with GlobalFoundries' 130nm low-power process and Tezzaron's 3D TSV technology. The 3D implementation shows that the 3D ICs can alleviate the pressure from I/O pin count and allow parallel memory accesses through multiple channels.
