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System-Level Modeling of a NoC-Based H.264 Decoder
BibTeX
@MISC{Agarwal_system-levelmodeling,
author = {Ankur Agarwal and Cyril-Daniel Iskander and Hari Kalva and Ravi Shankar},
title = {System-Level Modeling of a NoC-Based H.264 Decoder},
year = {}
}
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Abstract
Abstract -Networks-on-chip (NoC) are expected to play a key role in future embedded systems. A NoC-based system has the potential to support concurrent processing, in both software and hardware. This can however lead to concurrency issues. We present a multiprocessor system modeling and performance evaluation approach that addresses concurrency. We illustrate our methodology by mapping a H.264 decoder onto a 4×3 meshbased NoC architecture. We show latency, area, and power consumption results for this NoC architecture abstracted from its FPGA implementation.
