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Itanium — a system implementor’s tale (2005)
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| Venue: | In Proc. 2005 USENIX Techn. Conf |
| Citations: | 11 - 5 self |
BibTeX
@INPROCEEDINGS{Gray05itanium—,
author = {Charles Gray and Matthew Chapman and Peter Chubb and David Mosberger-tang and Gernot Heiser},
title = {Itanium — a system implementor’s tale},
booktitle = {In Proc. 2005 USENIX Techn. Conf},
year = {2005},
pages = {264--278}
}
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Abstract
Itanium is a fairly new and rather unusual architecture. Its defining feature is explicitly-parallel instruction-set computing (EPIC), which moves the onus for exploiting instruction-level parallelism (ILP) from the hardware to the code generator. Itanium theoretically supports high degrees of ILP, but in practice these are hard to achieve, as present compilers are often not up to the task. This is much more a problem for systems than for application code, as compiler writers ’ efforts tend to be focused on SPEC benchmarks, which are not representative of operating systems code. As a result, good OS performance on Itanium is a serious challenge, but the potential rewards are high. EPIC is not the only interesting and novel feature of Itanium. Others include an unusual MMU, a huge register set, and tricky virtualisation issues. We present a number of the challenges posed by the architecture, and show how they can be overcome by clever design and implementation. 1
Keyphrases
system implementor tale present compiler good o performance serious challenge novel feature instruction-level parallelism tricky virtualisation issue defining feature unusual architecture explicitly-parallel instruction-set computing compiler writer effort high degree clever design system code potential reward code generator unusual mmu spec benchmark application code huge register
