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Hardware Accelerated Power Estimation (2005)
| Citations: | 2 - 1 self |
BibTeX
@MISC{Coburn05hardwareaccelerated,
author = {Joel Coburn and Srivaths Ravi and et al.},
title = { Hardware Accelerated Power Estimation},
year = {2005}
}
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Abstract
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given design with “power estimation hardware”, map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial designs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools.
Keyphrases
power emulation hardware accelerated power estimation hardware acceleration test stimulus power estimation power estimation hardware fast power estimation significant speedup power consumption estimate prototyping platform industrial design power estimation tool empirical study state-of-the-art commercial register-transfer level power model evaluation hardware circuit novel design paradigm
