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A Comparison of Evolvable Hardware Architectures for Classification Tasks
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| Venue: | In Proceedings 8th International Conference on Evolvable Systems (ICES |
| Citations: | 5 - 3 self |
BibTeX
@INPROCEEDINGS{Glette_acomparison,
author = {Kyrre Glette and Jim Torresen and Paul Kaufmann and Marco Platzner},
title = {A Comparison of Evolvable Hardware Architectures for Classification Tasks},
booktitle = {In Proceedings 8th International Conference on Evolvable Systems (ICES},
year = {}
}
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Abstract
Abstract. We analyze and compare four different evolvable hardware approaches for classification tasks: An approach based on a programmable logic array architecture, an approach based on two-phase incremental evolution, a generic logic architecture with automatic definition of building blocks, and a specialized coarse-grained architecture with pre-defined building blocks. We base the comparison on a common data set and report on classification accuracy and training effort. The results show that classification accuracy can be increased by using modular, specialized classifier architectures. Furthermore, function level evolution, either with predefined functions derived from domain-specific knowledge or with functions that are automatically defined during evolution, also gives higher accuracy. Incremental and function level evolution reduce the search space and thus shortens the training effort. 1
Keyphrases
classification task evolvable hardware architecture function level evolution classification accuracy training effort domain-specific knowledge search space two-phase incremental evolution generic logic architecture programmable logic array architecture common data set classifier architecture pre-defined building block different evolvable hardware approach predefined function automatic definition building block specialized coarse-grained architecture
