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Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores (2005)
| Citations: | 15 - 3 self |
BibTeX
@MISC{Zhuo05designingscalable,
author = {Ling Zhuo and et al.},
title = {Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores},
year = {2005}
}
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Abstract
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when using single-cycle arithmetic cores. In particular, the data hazards associated with pipelined floating-point reduction circuits can limit the scalability or severely reduce the performance of an otherwise high-performance computational kernel. The inability to efficiently execute the reduction in hardware coupled with memory bandwidth issues may even negate the performance gains derived from hardware acceleration of the kernel. In this paper we introduce a method for developing scalable floating-point reduction circuits that run in optimal time while requiring only Θ(lg(n)) space and a single pipelined floating-point unit. Using a Xilinx Virtex-II Pro as the target device, we implement reference instances of our reduction method and present the FPGA design statistics supporting our scalability claims.
Keyphrases
scalable fpga-based reduction circuit using floating-point core optimal time floating-point unit target device fpga design statistic single-cycle arithmetic core high-performance computational kernel scalable floating-point reduction circuit scalability claim pipelined floating-point arithmetic core pipelined floating-point reduction circuit new class hardware acceleration reduction method performance gain xilinx virtex-ii pro data hazard high-performance fpga-based computational kernel memory bandwidth issue reference instance
