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Sparse matrix-vector multiplication on FPGAs (2005)
| Venue: | In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays |
| Citations: | 60 - 7 self |
BibTeX
@INPROCEEDINGS{Zhuo05sparsematrix-vector,
author = {Ling Zhuo and Viktor K. Prasanna},
title = {Sparse matrix-vector multiplication on FPGAs},
booktitle = {In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays},
year = {2005},
pages = {63--74},
publisher = {ACM Press}
}
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Abstract
Sparse matrix-vector multiplication (SpMXV) is a key computational kernel widely used in scientific applications and signal processing applications. However, the performance of SpMXV on most modern processors is poor due to the irregular sparsity structure in the matrices. Application-specific processors including FPGA-based systems have become promising alternatives to realize high performance sparse matrix computations. The abundant hardware resources on current FPGAs provide new opportunities to improve the performance of this kernel. In this paper, we propose a FPGA-based algorithm for floating-point SpMXV. Our algorithm employs a circular linear array architecture which can perform multiple floating-point operations in parallel. Our algorithm accepts sparse matrices in column-compressed format (CCF) as inputs, and does not have any requirements on the sparsity structure of the matrices. The architecture overlaps memory I/O time and computation time to improve the performance. The performance of our algorithm is evaluated using various sparse matrices used by the scientific computing community. Our target device is Xilinx Virtex-II Pro XC2VP100. Experimental results show that for 32-bit floating-point SpMXV, our algorithm achieves 1.2 GFLOPS with 6 PEs at a memory bandwidth of 5.6 GB/s. For 64-bit floating point SpMXV, our algorithm is able to achieve 950 MFLOPS at a memory bandwidth of 6.5 GB/s. These implementations use less than 15 % and 30 % of slices on XC2VP100, respectively. 1
Keyphrases
sparse matrix-vector multiplication memory bandwidth xilinx virtex-ii pro xc2vp100 irregular sparsity structure multiple floating-point operation application-specific processor fpga-based algorithm abundant hardware resource various sparse matrix target device modern processor signal processing application algorithm accepts sparse matrix point spmxv scientific application high performance sparse matrix computation 32-bit floating-point spmxv computation time key computational kernel promising alternative sparsity structure current fpgas scientific computing community floating-point spmxv fpga-based system experimental result circular linear array architecture column-compressed format new opportunity
